12/24/2022 0 Comments Doxygen verilog![]() ![]() In this tutorial, we will add a simple two-terminal device to Xyce that internally simulates a resistor, capacitor, and inductor in series. This page does not include any Verilog-A instruction. This section assumes you are already familiar with the Verilog-A language and are comfortable developing compact models in this language. Xyce does have a limited beta capability using shared-library "plug-ins" to add models at run time, but building these plug-ins still requires access to the full Xyce source code tree because the plugin capability is not enabled by default and is not present in any binary release of Xyce.Īdding a device to Xyce through Verilog-A In either case, you must be building Xyce from source code in order to add models to it. ![]() Simply type "doxygen Doxyfile" in the doc/doxygen directory, and it will produce files in the "html" subdirectory that may be browsed with a web browser (open html/index.html first). Note: The doxygen documentation is no longer provided in source tarballs, as it was determined that it inflated the download size and was of limited interest to most users, but may be generated if you have Doxygen and graphviz installed on your system. ![]() The RLC device created through the Verilog-A translation process is another implementation example. ![]() The "Circuit Device How To…" page in the Doxygen documentation describes the basic functions you must provide, and points you at the resistor and capacitor devices as sample implementations. Then consult the Doxygen documentation that can be generated in the doc/doxygen directory of the Xyce source tree. If you are interested in developing C++ compact models in Xyce, you should still review the Verilog-A method and look at the C++ source code it generates. This tutorial will not describe that technique. The tutorial will show one approach to adding this device: implementation of the compact model in Verilog-A, converting this model to C++ code that can be used in Xyce by using ADMS with the Xyce/ADMS back-end, and adding the new model to Xyce.ĭirect implementation of the compact model in C++ and adding the new model to Xyce is more difficult, and requires a more thorough understanding of the Xyce code structure. The demonstration model will implement a two-terminal device that simulates a simple series RLC combination. This tutorial will show an example of how to add a very simple device model to Xyce. A separate document, the Xyce/ADMS Users’ Guide, provides a simpler process that was introduced with Xyce 6.5, and documents the capabilities of the Xyce/ADMS Verilog compiler. This document is a more in-depth discussion of the process of adding a compact model in Verilog-A to Xyce, explaining how to wire a device into Xyce permanently and also how to create a shared-library plugin. It is assumed here that you are already a compact model developer and that you are only reading this to learn the specifics of how to get your model coded in Xyce. It is assumed that you already know how to build Xyce, and that you are comfortable using your operating system’s editors. You should be familiar with the Xyce Mathematical Formulation before attempting to add a device model to Xyce. The target audience is compact model developers. It is being retained in the documentation section because it is not strictly limited to adding device models through a Verilog-A process, but is not regularly updated as Xyce development proceeds. NOTE: This document has largely been superseded by the Xyce/ADMS Users’ Guide. This tutorial is intended as a brief introduction to adding a device model to the Xyce™ Parallel Electronic Simulator. ![]()
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